OFDM transmission apparatus and method having minimal transmission delay

ABSTRACT

An OFDM transmission apparatus having minimal transmission delay comprises a training symbol storage and generation unit, a delay unit and a controller. The training symbol storage and generation unit stores training symbols for the preamble, and outputs the stored training symbols when a training symbol output request signal is received. The delay unit receives data for the signal field from the MAC layer, delays the received data by the data processing time of the scrambler, and outputs the delayed data to the convolution encoder. The controller outputs the training symbol output request signal, requesting the preamble of the frame, to the training symbol storage and generation unit when a frame transmission request is received from the MAC layer, and outputs a data request signal, requesting the signal field and the data field, to the MAC layer in consideration of total data processing time (T PROCESS ).

RELATED APPLICATIONS

The present application is based on, and claims priority from, KoreanApplication Number 2004-0086741, filed Oct. 28, 2004, the disclosure ofwhich is incorporated by reference herein in its entirety. Thisapplication is a REI of 11/115,585 Apr. 26, 2005 U.S. Pat. No.7,417,946.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to an orthogonal frequencydivision multiplexing transmission technology and, more particularly, toan orthogonal frequency division multiplexing transmission apparatus andmethod that are implemented to minimize the transmission delay of aframe when the frame received from an upper layer is transmitted.

2. Description of the Prior Art

Recently, Internet telephones have been popularized, and severalwireless Internet telephones using Wireless Local Area Network (WLAN)technologies based on the IEEE 802.11 standard have been commercialized.

One of the factors that must be considered to apply WLAN technologies tovoice communication is a transmission delay problem. If the transmissiondelay between transmitting and receiving parties in voice communicationis long, an echo may be generated and degrade the quality ofcommunication. Accordingly, efforts to minimize transmission delay asmuch as possible must be made.

An OFDM scheme, that is, one of the WLAN technologies, is a digitalmodulation scheme for improving a transmission rate per unit bandwidthand preventing multi-path interference, and is a multi-carriermodulation scheme using a plurality of carriers that are orthogonal toone another. Furthermore, the OFDM scheme allows many carriers to bemultiplexed compared to a common Frequency Division Multiplexing (FDM)scheme, so that the OFDM scheme has high frequency use efficiency and atransmission rate per unit bandwidth can be increased when the number ofcarriers increases.

A typical implementation example in which a transmitter is implementedusing such an OFDM scheme is shown in FIG. 1. Generally, in an OFDMtransmitter, data to be transmitted are transmitted to a scrambler 101with a transmission rate set thereon. The data scrambled in thescrambler 101 are input to an interleaver 103 through a convolutionencoder 102. The data are interleaved with each other in the interleaver103. A constellation mapper 104 maps the interleaved data according to atransmission data rate, and then transmits the mapped data to a RadioFrequency (RF) converter 108 through an inverse fast Fourier transformer105, a guard-interval inserter 106 and a symbol wave-shaping filter 107.

FIG. 2 is a schematic view illustrating the format of a frame that istransmitted from the OFDM transmitter of FIG. 1. When the frame shown inFIG. 2 is output through the OFDM transmitter of FIG. 1, a preamble 21is output as ten short training symbols during the first 8 μs(microseconds) and then as two long training symbols during a subsequent8 μs and a signal field 22 and a data field 23 are output as OFDMsymbols on a 4 μs (i.e., a transmission interval basis) basis, as shownin FIG. 3.

In order to implement such a transmitter to have minimal transmissiondelay, it is required that the training symbols shown in FIG. 3 beoutput from the transmitter immediately after a data transmissionrequest is generated. Although not particularly defined in the IEEE802.11 standard, to fulfill the above-described condition, thetransmitter must be constructed so that the training symbolscorresponding to the preamble 21 are previously stored in a trainingsymbol storage and generation unit 150, the training symbols are outputfrom the training symbol storage and generation unit 150 immediatelyafter a data transmission request is generated, and OFDM symbols thatcorrespond to the signal field 22 and the data field 23 are outputimmediately after the output of the training symbols is completed, asshown in FIG. 4.

Conventionally, there is no particular requirement for how the OFDMtransmitter is implemented so as to have minimal transmission delay. Theconstruction of the OFDM transmitter shown in FIG. 4 may have adifferent purpose, and can be easily contrived by any person having abasic knowledge of electronic or communication engineering on the basisof the IEEE 802.11 standard.

An example of such construction is disclosed in U.S. Pat Appl. Pub No.2004/0160892 A1 (published on Aug. 19, 2004) entitled “OrthogonalFrequency Division Multiplexing Transmitter System and VLSIImplementation Thereof.” The system of the preceding patent isconstructed in such a way that a time-domain preamble is previouslystored in a memory, and is then transmitted without passing throughother function blocks immediately after a data transmission request isgenerated. However, the preceding patent discloses only that very smalltransmission delay is achieved by causing the preamble to be directlyoutput without passing through other function blocks, but does notdisclose the time points at which a signal field and a data field willbe output in consideration of the data processing of other functionblocks. In other words, the preceding patent does not describe the timepoints at which the data of the signal field and the data field arerequested from an upper layer while the training symbols of the preambleare output, in consideration of the data processing time of the functionblocks. Accordingly, the implementation of an OFDM transmitter havingminimal transmission delay, which the present invention attempts toachieve, has not been disclosed.

Meanwhile, an OFDM modulation/demodulation apparatus and method, whichsupport a variable data rate in a WLAN system, are disclosed in KoreanPat No. 0375824 issued on Feb. 28, 2003. This patent provides the OFDMmodulation/demodulation apparatus and method that can support a variabledata rate prescribed in the IEEE 802.11a standard. In particular, theapparatus and method allow modulation and demodulation based on a datarate of 6 Mbps to 54 Mbps to be processed in a single device. However,this OFDM modulation/demodulation apparatus does not teach a method ofimplementing a transmission apparatus having minimal transmission delay.

SUMMARY OF THE INVENTION

The present invention provides an OFDM transmission apparatus and methodhaving minimal transmission delay, which can output previously storedtraining symbols when a frame transmission request is received from anupper layer, and can output signal and data field request signals to theupper layer while the training symbols are output in consideration ofthe data processing time of function blocks so that the OFDM symbols ofthe signal and data fields are output immediately after the output ofthe training symbols is completed, thus minimizing transmission delay atthe time of transmitting a frame.

The present invention provides an OFDM transmission apparatus havingminimal transmission delay, the apparatus having a scrambler, aconvolution encoder, an interleaver, a constellation mapper, an inversefast Fourier transformer, a guard-interval inserter, a symbolwave-shaping filter and an RF converter, and transmitting a framecomposed of a preamble, a signal field and a data field that arereceived from a MAC layer, that is, an upper layer, including a trainingsymbol storage and generation unit for storing training symbols for thepreamble, and outputting the stored training symbols when a trainingsymbol output request signal is received; a delay unit for receivingdata for the signal field from the MAC layer, delaying the received databy the data processing time of the scrambler, and then outputting thedelayed data to the convolution encoder; and a controller for outputtingthe training symbol output request signal, requesting the preamble ofthe frame, to the training symbol storage and generation unit when aframe transmission request is received from the MAC layer, andoutputting a data request signal, requesting the signal field and thedata field, to the MAC layer in consideration of the total dataprocessing time (T_(PROCESS)) required by components ranging from thescrambler to the guard-interval inserter; wherein the scramblerscrambles the received data for the data field of the transmitted frame,and then transmits the scrambled data to the convolution encoder.

The controller outputs the data request signal requesting the signalfield to the MAC layer [total time required to output trainingsymbols−T_(PROCESS)] after a time point at which the training symbolsare output from the training symbol storage and generation unit.

In accordance with an embodiment of the present invention, the OFDMtransmission apparatus further includes a FIFO unit that is providedwith dual-port Random Access Memory (RAM) for storing the data, that isplaced in front of the constellation mapper, and that differentlyprocesses a clock used to write the data into the dual-port RAM and aclock used to read the data from the dual-port RAM. In this case, thedelay unit, the scrambler, the convolution encoder, the interleaver andthe controller, which correspond to components located in front of theFIFO unit, may use a clock identical to a clock that is used when dataare written into the FIFO unit; and the constellation mapper, theinverse fast Fourier transformer, the guard-interval inserter, thetraining symbol storage and generation unit and the symbol wave-shapingfilter, which correspond to components located behind the FIFO unit, mayuse a clock identical to a clock that is used when data are read fromthe FIFO unit.

In order to accomplish the above object, the present invention providesan OFDM transmission method having minimal transmission delay in an OFDMtransmission apparatus, the OFDM transmission apparatus having ascrambler, a convolution encoder, an interleaver, a constellationmapper, an inverse fast Fourier transformer, a guard-interval inserter,a symbol wave-shaping filter and an RF converter, and transmitting aframe composed of a preamble, a signal field and a data field that arereceived from a MAC layer, that is, an upper layer, including the firststep of calculating total data processing time (T_(PROCESS)) required bycomponents ranging from the scrambler to the guard-interval inserter andstoring training symbols of a preamble of a frame to be transmitted; thesecond step of outputting the stored training symbols when a frametransmission request signal is received from the MAC layer; the thirdstep of outputting a data request signal requesting a signal field ofthe frame to the MAC layer [total time required to output trainingsymbols−T_(PROCESS)] after a time point at which the training symbolsare output; the fourth step of delaying the data for the signal field,which is received from the MAC layer, by the processing time of thescrambler, and then outputting data for the signal field to theconvolution encoder; and the fifth step of outputting the data requestsignal requesting the data field of the frame to the MAC layer after atransmission interval that is set based on a time point at which thedata request signal requesting the signal field is output, and allowingthe scrambler to scramble the received data and then output thescrambled data to the convolution encoder when the data for the datafield are received from the MAC layer.

In accordance with an embodiment of the present invention, the OFDMtransmission method may further include the sixth step of calculatingtotal data processing time (T_(AFTERFIFO)) required by componentsranging from the constellation mapper to the guard-interval inserterthat correspond to components located behind the FIFO unit; the seventhstep of transmitting a FIFO access activation signal to theconstellation mapper [total time required to output trainingsymbols−T_(AFTERFIFO)] after a time point at which the training symbolsare output; and the eighth step of transmitting a data request signalfor reading data to the FIFO unit so that the FIFO unit outputs the datawhen the FIFO access activation signal is generated.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a schematic diagram illustrating the construction of a typicalOFDM transmitter based on the IEEE 802.11 standard;

FIG. 2 is a schematic diagram illustrating the format of a frame that istransmitted through the OFDM transmitter based on the IEEE 802.11standard;

FIG. 3 is a diagram illustrating the structure of OFDM symbols that areoutput from the OFDM transmitter based on the IEEE 802.11 standard;

FIG. 4 is a block diagram illustrating the typical construction of anOFDM transmitter having minimal transmission delay based on the IEEE802.11 standard;

FIG. 5 is a schematic diagram illustrating the construction of an OFDMtransmission apparatus having minimal transmission delay according to anembodiment of the present invention;

FIG. 6 is a diagram illustrating the correlation between transmissioninformation related to OFDM communication based on the IEEE 802.11standard according to the present invention;

FIG. 7 is a diagram illustrating the correlation between control signalsthat are output from a controller according to an embodiment of thepresent invention;

FIG. 8 is a chart illustrating a method of writing or reading data intoor from RAM in first and second permutation processes performed by theinterleaver in the OFDM transmitter based on the IEEE 802.11 standardaccording to the present invention;

FIG. 9 is a chart illustrating a method of reading data from a RAM infirst and second permutation processes performed by the interleaver inthe OFDM transmitter based on the IEEE 802.11 standard according to thepresent invention;

FIG. 10 is a diagram showing the correlation between control signals forwriting or reading data into or from the RAM of the interleaveraccording to the present invention;

FIG. 11 is a diagram illustrating the correlation between signals forcontrolling the output of the constellation mapper according to anembodiment of the present invention;

FIG. 12 is a chart illustrating a constellation mapping scheme in theOFDM transmitter based on the IEEE 802.11 standard according to thepresent invention;

FIG. 13 is a diagram illustrating the correlation between controlsignals for writing or reading into or from a dual-port RAM in aguard-interval inserter having the dual-port RAM according to anembodiment of the present invention;

FIG. 14 is a flowchart illustrating an OFDM transmission method havingminimal transmission delay according to an embodiment of the presentinvention; and

FIG. 15 is a flowchart illustrating an OFDM transmission method for aFIFO operation according to an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference now should be made to the drawings, in which the samereference numerals are used throughout the different drawings todesignate the same or similar components.

When an OFDM transmission apparatus and method according to the presentinvention are described below, the components of the conventional OFDMtransmitter, which are shown in FIGS. 1 to 4 and can be applied to thepresent invention in the same manner, will be used without change forease of description. Furthermore, the format of the frame that istransmitted from the OFDM transmission apparatus, the training symbolsand the OFDM symbols, which are shown in FIGS. 1 to 4, will be used forthe description of the present invention.

FIG. 5 is a schematic diagram illustrating the construction of an OFDMtransmission apparatus having minimal transmission delay according to anembodiment of the present invention. As shown in FIG. 5, the OFDMtransmission apparatus 100 having minimal transmission delay accordingto the present invention includes a delay unit 110, a scrambler 101, acontroller 130, a convolution encoder 102, an interleaver 103, a FIFO(First-In First-Out) unit 140, a constellation mapper 104, an inversefast Fourier transformer 105, a guard-interval inserter 106, a trainingsymbol storage and generation unit 150, a symbol wave-shaping filter 107and a Radio Frequency (RF) converter 108. In this case, the FIFO unit140 is used to provide flexibility to the use of clocks by thetransmission apparatus 100, and may be omitted depending on the design.Reference numerals 120 and 160 designate signal selectors.

The OFDM transmission apparatus 100 shown in FIG. 5 according to thepresent invention exchanges data with an upper-layer processor.Preferably, the OFDM transmission apparatus 100 exchanges data with aMedia Access Control (MAC) layer (not shown) that generates a signalfield and a data field, which constitute an OFDM frame, or receives asignal field and a data field in response to an external control signal.Accordingly, the controller 130 of the OFDM transmission apparatus 100according to the present invention receives a frame data transmissionrequest from the MAC layer, extracts a data rate (RATE) and a datalength (LENGTH) from a signal field, and outputs a signal field datarequest signal to the MAC layer. Furthermore, the delay unit 110 of theOFDM transmission apparatus 100 according to the present inventionreceives signal field data from the MAC layer. The scrambler 101receives data field data from the MAC layer. This operation is describedin detail below.

A detailed operation of the OFDM transmission apparatus 100 havingminimal transmission delay according to the present invention isdescribed in detail with reference to FIGS. 2 to 5.

The controller 130 controls the output of training symbols, requests thesignal field 22 of the frame 200, which will be transmitted, from theMAC layer, that is, an upper layer, extracts RATE and LENGTH from thesignal field 22, requests the data field 23 of the frame 200, which willbe transmitted, from the MAC layer, and controls the time points atwhich the training symbols of the preamble and the OFDM symbols of thesignal and data fields are output. The controller 130 transmits atraining symbol output request signal to the training symbol storage andgeneration unit 150 immediately after a frame data transmission requestsignal 52 is generated by the MAC layer. That is, the training symbolstorage and generation unit 150 stores the training symbols of a frameto be transmitted, and outputs the stored training symbols when thetraining symbol output request signal is received from the controller130. As described above, the controller 130 according to the presentinvention generates the training symbol output request signalimmediately after the frame data transmission request signal isgenerated by the upper layer, so that the training symbols can be outputwithout time delay. Accordingly, the OFDM transmission apparatus 100 ofthe present invention can reduce transmission delay. The trainingsymbols are composed of ten short training symbols, a guard intervalcorresponding to 1.6 μs, and two long training symbols, as shown in FIG.3. The interval of a training symbol is 16 μs, as shown in FIG. 3. Theinterval of the training symbol (the total time required to output thetraining symbols) conforms to the IEEE 802.11 standard, but may bevariously set if necessary.

Referring to FIG. 5, the signal field 22 of the frame 200 shown in FIG.2 is input to the convolution encoder 102 through the delay unit 110without passing through the scrambler 101. In contrast, the data field23 of the frame 200 passes from the scrambler 101 through all thefunction blocks 102 to 108 except the delay unit 110, the controller 130and the training symbol storage and generation unit 150. In order forthe transmission apparatus 100 to have minimal transmission delay, it isrequired that OFDM symbols corresponding to the signal field be outputimmediately after the training symbols are output in such a way as torequest the signal field 22 and the data field 23 from the upper layerwhile the training symbols are output in consideration of the dataprocessing time of the function blocks of the transmission apparatus100. Accordingly, the controller 130 outputs a control signal, whichindicates readiness for the transmission of the signal field 22, to theMAC layer so that the data of the signal field 22 can be transmitted.The signal field 22 of the frame 200 is composed of RATE, Reserved,LENGTH, Parity and Tail, as shown in FIG. 2. In this case, RATEindicates a data rate at which data is processed in the transmissionapparatus 100 of FIG. 5, as shown in FIG. 6 (that conforms to the IEEE802.11a standard). In the frame 200, a Physical Layer ConvergenceProtocol Service Data Unit (PSDU) is composed of octet-based data, andLENGTH indicates the number of octets. A constellation mapping schemethat is performed in the constellation mapper 104 and the number of databits that are contained in each OFDM symbol vary with the RATE. Forexample, in the example of the frame 200 shown in FIG. 2, the signalfield 22 has a data rate of 6 Mbps, employs a BPSK constellation mappingscheme, and is 24-bit data. Accordingly, in this case, as in FIG. 7, acontrol signal indicating readiness for the transmission of the signalfield is activated during the interval to receive 24-bit datacorresponding to the signal field 22. The 24-bit data corresponding tothe signal field 22, which is input to the transmission apparatus 100 ofthe present invention in response to the control signal indicatingreadiness for the transmission of the signal field, is input to thecontroller 130 and the convolution encoder 102 in the same manner. Thecontroller 130 performs control so that the convolution encoder 102processes the data of the signal field 22, not the output of thescrambler 101. That is, the signal field 22 is processed through thedelay unit 110, the convolution encoder 102, the interleaver 103, theFIFO unit 140, the constellation mapper 104, the inverse fast Fouriertransformer 105, the guard-interval inserter 106, the symbolwave-shaping filter 107, and the RF converter 108.

If the total processing time required by the convolution encoder 102,the interleaver 103, the FIFO unit 140, the constellation mapper 104,the inverse fast Fourier transformer 105 and the guard-interval inserter106 in the transmission apparatus 100 shown in FIG. 5 according to thepresent invention is assumed to be T_(SIG), the controller 130 mustgenerate a control signal indicating readiness for the transmission ofthe signal field so that the data of the signal field 22 can be input tothe convolution encoder 102 [16 μs−T_(SIG)] after the time point atwhich training symbols are output from the training symbol storage andgeneration unit 150. However, in order for the control signal indicatingreadiness for the transmission of the signal field or data field to begenerated at 4-μs intervals, that is, transmission intervals, it isrequired that after the control signal indicating readiness for thetransmission of the signal field has been generated and before the dataof the signal field 22, which are input to the transmission apparatus100, is input to the convolution encoder 102, the data of the signalfield 22 be delayed through the delay unit 110 by the processing time ofthe scrambler 101 and then input to the convolution encoder 102.Furthermore, when the total data processing time of the scrambler 101,the convolution encoder 102, the interleaver 103, the FIFO unit 140, theconstellation mapper 104, the inverse fast Fourier transformer 105 andthe guard-interval inserter 106 in the transmission apparatus 100 isassumed to be T_(PROCESS) (<16 μs), it is required that the controller130 generate the control signal, which indicates readiness for thetransmission of the signal field, [16 μs−T_(PROCESS)] after the timepoint at which the training symbols are output from the training symbolstorage and generation unit 150, as shown in FIG. 7. In this case, theabove-referenced 16 μs refers to the total time required to output thetraining symbols, as shown in FIG. 2, and is the same hereinafter.

Furthermore, in order for the guard-interval inserter 106 to output OFDMsymbols corresponding to the signal field 22 and the data field 23 atthe time point at which the training symbol storage and generation unit150 completes the generation of the training symbols, when the totaldata processing time of the constellation mapper 104, the inverse fastFourier transformer 105 and the guard-interval inserter 106 in thetransmission apparatus 100 is assumed to be T_(AFTERFIFO), it isrequired that the controller 130 transmit a signal indicating FIFOaccess activation to the constellation mapper 104 [16 μs−T_(AFTERFIFO)]after the time point at which the training symbols are output from thetraining symbol storage and generation unit 150, and that theconstellation mapper 104 transmit a FIFO data request signal, whichcommands that data be read from the FIFO unit 140, to the FIFO unit 140when the FIFO access activation signal is received, thus starting toprocess data output from the FIFO unit 140, as shown in FIG. 7.

The controller 130 acquires and stores RATE and LENGTH information fromthe signal field 22 that is input by the MAC layer. As shown in FIG. 7,the controller 130 generates a control signal indicating readiness forthe transmission of the data field, as shown in FIG. 5, so as to receivedata corresponding to the data field 23 of the frame 200 of FIG. 2 4 μs,that is, a transmission interval, after the time point at which thecontrol signal indicating readiness for the transmission of the signalfield is generated. The activation interval (T_(DBPS)) of the controlsignal indicating readiness for the transmission of the data field mustbe maintained so that data the number of which is identical to thenumber of bits N_(DBPS) corresponding to one OFDM symbol can be inputfrom the MAC layer to the transmission apparatus 100 of the presentinvention according to the RATE information, as shown in FIG. 6. In thiscase, in order to receive the data corresponding to the data field 23 ofthe frame 200 4 μs, that is, the transmission interval, after the timepoint at which the control signal indicating readiness for thetransmission of the signal field is generated, the above-describedprocess is repeated. Furthermore, according to the LENGTH information,the process is repeated at 4-μs intervals until the entire data field 23including SERVICE, PSDU, Tail and Pad Bits is input to the transmissionapparatus 100, as shown in FIG. 2.

The request for the data field 23 is described in more detail below. Inthe frame 200, the data request signal requesting the data field 23 isgenerated at 4-μs intervals. A valid interval for the data requestsignal may vary with the RATE information. The repetition of thegeneration of the data request signal is dependent upon the LENGTHinformation. That is, since information on how many bytes are used toconstruct the data field 23 when the MAC layer constructs the frame 200is contained in the LENGTH information, the data request signalrequesting the data field 23 is repeatedly generated at 4-μs intervals,that is, the transmission intervals, until all of the data of the datafield corresponding to the length is received. Furthermore, whenever thetransmission of a frame begins, a data rate RATE is determined in theupper layer. One is selected from eight data rates shown in FIG. 6 andinformation about the data rate is contained in the RATE information.The length of the data request signal (the length indicating the validinterval) requesting the data field 23 shown in FIG. 7 varies with theRATE information. Accordingly, until all the data contained in the frame200 to be currently transmitted are transmitted, a process, in which thedata request signal requesting the data field 23 is transmitted to theMAC layer at preset periods and the scrambler 101 scrambles receiveddata and then outputs the scrambled data to the convolution encoder 102when the data of the data field 23 is received from the MAC layer, isrepeated.

As described above, the scrambler 101 receives only the data field 23 ofthe frame 200 to be transmitted from the MAC layer, scrambles the datafield 23, and then outputs the scrambled data to the convolution encoder102. Furthermore, the delay unit 110 receives only the signal field 22of the frame from the MAC layer, delays the signal field 22 by the dataprocessing time of the scrambler 101, and then outputs the delayedsignal field 22. That is, when the time ranging from the time point atwhich the data field 23 is input to the scrambler 101 to the time pointat which the data field 23 is output from the scrambler 101 is assumedto be T_(SCRAMBLER), the delay unit 110 delays the received signal field22 by T_(SCRAMBLER), and then outputs the delayed signal field to theconvolution encoder 102.

The scrambler 101 is used to prevent the generation of long intervalshaving the same values in a data string to be transmitted. The scrambleris implemented based on a generator polynomial S(x)=x⁷+x⁴+1 thatconforms to the IEEE 802.11 standard. When the scrambler is implementedusing hardware, it can be implemented using a shift register, which usesa flip-flop, and a digital logic circuit. The scrambler 101 generates abit string corresponding to 1 or 0 based on the generator polynomial,performs an exclusive OR operation on the bit string and a data bitstring input to the scrambler 101, and outputs the operation results.

The convolution encoder 102 is used to allow a receiver to correct anerror when the error occurs in a transmitted data string. Theconvolution encoder 102 is implemented based on generator polynomialsg₀=133₈ and g₁=171₈ that conform to the IEEE 802.11 standard. When theconvolution encoder 102 is implemented using hardware, it can beimplemented using a shift register, which uses a flip-flop, and adigital logic circuit. The convolution encoder 102 generates a bitstring corresponding to 1 or 0 based on the generator polynomials,performs an XOR operation on the bit string and a data bit string inputto the convolution encoder 102, and then outputs the operation results.Furthermore, it is preferred that the output of the convolution encoder102 be output in a 2-bit parallel manner because the results of the twogenerator polynomials exist in parallel.

The interleaver 103 is used to convert burst errors into small randomerrors that are distributed to various locations, in consideration ofthe fact that the burst errors, which are concentrated at somelocations, occur while data is transmitted via a transmission medium.The interleaver 103 performs a first permutation process and a secondpermutation process. The first permutation process is implemented basedon a permutation equation i=(N_(CBPS)/16(k mod 16)+floor(k/16) (wherek=0, 1, . . . , N_(CBPS)−1) that conforms to the IEEE 802.11 standard.The second permutation process is implemented based on a permutationequation j=s×floor(i/s)+(i+N_(CBPS)−floor(16×i/N_(CBPS))) mod s (wherei=0, 1, . . . , N_(CBPS)−1) that conforms to the IEEE 802.11 standard.In the two permutation equations, k is each bit index of a bit stringbefore the first permutation process, i is an index at which a bitlocated at a kth location before the first permutation process islocated after the first permutation process, j is an index at which abit located at an ith location before the second permutation process islocated after the second permutation process, mod is a modulo operation,floor( ) is the largest integer that does not exceed the value inparentheses, N_(CBPS) is the number of coded bits per OFDM symbol,s=max(N_(BPSC)/2,l), N_(BPSC) is the number of coded bits persub-channel that constitutes an OFDM transmission band, and max( ) isthe largest value in parentheses.

When the interleaver 103 is implemented using hardware, it isconstructed using Random Access Memory (RAM) and an interleavercontroller for writing or reading data into or from the RAM. In order toperform the first and second permutation processes, the sequence inwhich data are written into or read from the RAM must be the same asthat shown in FIG. 8. However, this is only an example for describingthe first and second permutation processes. In order to systematicallyimplement the interleaver 103, the constellation mapper 104, which is afunction block next to the interleaver, must be considered. Theconstellation mapper 104 groups a maximum of 3 bits and represents themusing a single real number to construct an inphase component and aquadrature component. In consideration of this, the number of bits,which are simultaneously output when data are output from the RAM, canbe determined according to a constellation mapping scheme. Accordingly,in the interleaver 103, one bit is output from the RAM at a time in thecase of BPSK, two bits are output from the RAM at a time in the case ofQPSK, four bits are output from the RAM at a time in the case of 16-QAM,and six bits are output from the RAM at a time in the case of 64-QAM.This will be described in more detail below.

When an index indicating the position in the sequence in which data areoutput from a RAM is assumed to be n (=0, 1, . . . , 47) and a locationwhere each of the bits is located when the bits output at the same timeare input to the constellation mapper is assumed to be b (=0, 1, 2, 3,4, 5), data are output from RAM in the manner shown in FIG. 9 when theindex and location of a bit are represented as n_(b) at the time atwhich data are output from the RAM. As shown in FIG. 9, the sequence inwhich data are output from the RAM may vary with a method ofimplementing an inverse fast Fourier transformer in consideration of asub-carrier frequency allocation scheme defined in the standard. Inorder to implement the scheme shown in FIG. 9, the RAM must be dividedinto at least 6 blocks.

Referring to FIG. 6, since the number of bits written into the RAMaccording to the constellation mapping scheme is N_(CBPS), the timetaken to write data into the RAM is also proportional to N_(CBPS). Indetail, the time taken to write data into the RAM is determineddepending on the scheme by which the convolution encoder 102 outputsdata and N_(CBPS) which is based on a transmission data rate RATE. Whenthe output of the convolution encoder 102 is output in a two-bitparallel manner as described above, the time taken to write the datainto the RAM is N_(CBPS)×0.5 BT (Bit Time). For example, in the case of16-QAM, in which a 40 MHz clock is used and a data rate is 24 Mbps,N_(CBPS)=192, so that the time taken to write data into the RAM is192×0.5×0.025=2.4 μs. However, in the case of 16-QAM, in which theoutput of the convolution encoder 102 is output in a 1-bit serial mannerand a data rate is 24 Mbps, the time is 192×0.025=4.8 μs when a 40-MHzclock is used. Accordingly, since only the time taken to write the datainto the RAM exceeds a 4-μs interval, a clock that is faster than the40-MHz clock must be used. As described above, when bits aresimultaneously output according to a constellation mapping scheme at thetime of the output of data from the RAM, the time taken for the RAM toread data is constant. This is described in more detail below.

If the time taken for the RAM to read data is calculated inconsideration of the total number of bits that are written into the RAMaccording to a constellation mapping scheme, versus the number of bitsthat are simultaneously output when the data are output from the RAM,the time is 48 BT in the case of BPSK, 96/2 BT in the case of QPSK,192/4 BT in the case of 16-QAM, and 288/6 BT in the case of 64-QAM. Asdescribed above, the time taken for the RAM to read the data is constantfor all the constellation mapping schemes. In order to keep T_(PROCESS)constant for all the constellation mapping schemes, the controller setsthe time point at which data are read from the RAM to the same timepoint for all the constellation mapping schemes on the basis of the timepoint at which the data are written into the RAM, as shown in FIG. 10.However, the time ranging from the time point at which data begins to bewritten into the RAM to the time point at which the last data are readfrom the RAM must be less than 4 μs.

The FIFO unit 140 is used to provide flexibility to the use of a clockin the transmission apparatus 100 of the present invention. The FIFOunit 140 is preferably composed of dual-port RAM 141 and a dual-port RAMcontroller 142. The dual-port RAM 141 generally includes a data inputport, a data output port, a read/write control input port, an operationclock input port, a chip actuation input port and a RAM access addressinput port, which are designed in a dual manner. Furthermore, memorycells, which correspond to the same physical location, can be accessedbased on RAM access addresses corresponding to respective ports.Accordingly, data can be read from the dual-port RAM 141 through oneport, while data are written into the dual-port RAM 141 through theother port. The clock used to write data and the clock used to read datacan be different. The dual-port RAM controller 142 controls both anoperation of writing data into the dual-port RAM 141 and an operation ofreading data from the dual port RAM 141. The clock used to write datainto the dual-port RAM 141 and the clock used to read data from thedual-port RAM 141 can be separate. That is, the delay unit 110, thescrambler 101, the convolution encoder 102, the interleaver 103 and thecontroller 130, which correspond to components located in front of theFIFO unit 140, use a clock identical to a clock that is used to writedata into the dual-port RAM 141 of the FIFO unit 140. The constellationmapper 104, the inverse fast Fourier transformer 105, the guard-intervalinserter 106, the training symbol storage and generation unit 150 andthe symbol wave-shaping filter 107 that correspond to components locatedbehind the FIFO unit, uses a clock identical to a clock that is used toread data from the dual-port RAM 141 of the FIFO unit 140. When data arewritten into the dual-port RAM, data generated by the interleaver 103and a control signal indicating a data valid interval are used. Whendata are output from the dual-port RAM, a FIFO data request signalgenerated by the constellation mapper is used.

The constellation mapper 104 functions to group a bit string into 1-bit,2-bit, 4-bit or 6-bit groups and represent he groups as one value so asto obtain a desired data rate based on the RATE information.Furthermore, the constellation mapper 104 also performs a null insertionfunction and a pilot insertion function. The constellation mapper 104transmits a FIFO data request signal to the FIFO unit 140 when a FIFOaccess activation signal is generated by the controller. Data input tothe constellation mapper 104 is separated into an inphase component anda quadrature component. Each of the inphase component and the quadraturecomponent is then grouped into 1-bit, 2-bit or 3-bit groups according toa constellation mapping scheme, and is then converted into a value. Theconstellation mapper 104 processes the data output from the interleaver103, so that when the interleaver that outputs data in the form shown inFIG. 9 is used, the constellation mapper 104 can separate received datainto an inphase component and a quadrature component without groupingthe data and process the received data according to a constellationmapping scheme.

When data input to the constellation mapper 104 are assumed to be n, thelocation of each of the bits that constitute the data n is assumed to beb (=0, 1, 2, 3, 4, 5), and a bit at the location b in data n is assumedto be n_(b), the constellation mapper 104 produces an inphase componentand a quadrature component in the same manner shown in FIG. 12. A nullinsertion location and a pilot insertion location can vary with themethod by which the interleaver 103 outputs data in consideration of asub-carrier frequency allocation method defined in the standard. Forexample, when a method by which the interleaver 103 outputs datacorresponds to a method 2 shown in FIG. 9, a null insertion location, apilot insertion location, and the interval location of data that isoutput from the FIFO unit can be controlled in the same manner as shownin FIG. 11. In this case, when a data request signal is transmitted tothe FIFO unit, it must be transmitted in the same manner as the framedata field signal of FIG. 11 is transmitted. In FIG. 11, numbersindicate corresponding indices when the numbers are output from theconstellation mapper.

The inverse fast Fourier transformer 105 performs a 64-Point InverseFast Fourier Transform (IFFT) function. Generally, when the size of IFFTor FFT can be represented as r^(m), r is called a radix. The radix istypically 2, 4 or 8. The inverse fast Fourier transformer 105 requiredfor the transmission apparatus 100 according to the present invention isnot greatly restricted by the processing time and the processing rate,so that the inverse fast Fourier transformer 105 can be implementedusing an inverse fast Fourier transformer having a typical pipelinestructure.

The guard-interval inserter 106 functions to insert a data stringcomposed of 16 pieces of data, which corresponds to a guard interval,before a data string composed of 64 pieces of data, which is output fromthe inverse fast Fourier transformer 105, and output a data stringcomposed of a total of 80 pieces of data. Generally, the 16 pieces ofdata corresponding to the guard interval employ data corresponding tolower 16 of the 64 pieces of data that are output from the inverse fastFourier transformer 105. The guard-interval inserter 106 can include RAMand a guard interval insertion controller. The total time ranging fromthe time point at which a data string input to the guard-intervalinserter 106 is written into the RAM to the time point at which the datastring is output along with the guard interval exceeds the OFDM symbolinterval 4 μs. Therefore, implementation is performed by dividing theRAM into two blocks or using dual-port RAM so that the interval in whicha data string corresponding to the 64 pieces of data, which are outputfrom the inverse fast Fourier transformer, is written into the RAM andthe interval in which the data string is output from the RAM can be 4μs. If the dual-port RAM is used, the clock used to write the datastring into the dual-port RAM and the clock used to read the data stringfrom the dual-port RAM are the same. In this case, write and readcontrol is performed in the same manner as shown in FIG. 13.

In FIG. 13, a data index indicates a position in the sequence in whichdata are transmitted in an OFDM symbol in a time domain after theinverse fast Fourier transformer 105 outputs the data. There is a casewhere data output from the inverse fast Fourier transformer 105 have abit-reversed index according to a method of implementing an inverse fastFourier transformer. In this case, a process in which data are made tohave a correct transmission sequence in a time domain is necessary,which can be easily achieved by controlling a write address. Theinterval between data strings that are output from the guard-intervalinserter 106 is set to 0.05 μs (=1/20 MHz). For example, when a clockused for function blocks that correspond to the components locatedbehind the FIFO unit is 40 MHz, the guard-interval inserter must outputthe same data twice.

The training symbol storage and generation unit 150 functions to storetraining symbols shown in FIG. 3 in a storage device such as ROM (ReadOnly Memory), and output the stored training symbols when the trainingsymbol output request signal is generated by the controller 130. Thetraining symbols are composed of OFDM symbols that are obtained byperforming an IFFT operation on the PLCP preamble 21 shown in FIG. 2using the inverse fast Fourier transformer 105. The training symbolstorage and generation unit 150 can include ROM and a training symbolgenerating controller.

The symbol wave-shaping filter 107 is used to reduce the spectralsidelobe of a frequency spectrum that is generated on a transmissionmedium through the transmission apparatus 100. The symbol wave-shapingfilter 107 can be implemented in the form of a time domain window thatis defined in the standard, or in the form of a Finite Impulse Response(FIR) filter having a common low pass function.

The RF converter 108 functions to move a data transmission band to afrequency band that is used to transmit data on a transmission medium.

FIG. 14 is a flowchart illustrating an OFEM transmission method havingminimal transmission delay according to an embodiment of the presentinvention. The flowchart shown in FIG. 14 can be preferably implementedin the above-described OFDM transmission apparatus. The OFDMtransmission method having minimal transmission delay according to thepresent invention is described with reference to the above-describeddrawings and FIG. 14 below.

As described above, the OFDM transmission apparatus 100, including thescrambler 101, the convolution encoder 102, the interleaver 103, theconstellation mapper 104, the inverse fast Fourier transformer 105, theguard-interval inserter 106, the symbol wave-shaping filter 107, the RFconverter 108, the delay unit 110, the controller 130 and the trainingsymbol storage and generation unit 150, exchanges data and signals witha MAC layer, and receives a transmission frame 200 from the MAC layerand transmits the transmission frame 200 to the next stage. Thetransmission frame 200 is composed of a preamble, a signal field and adata field. Referring to FIG. 14, the controller 130 calculates thetotal data processing time (T_(PROCESS)) required by the componentsranging from the scrambler 101 to the guard-interval inserter 106through the interleaver 103, the constellation mapper 104 and theinverse fast Fourier transformer 105 at step S10. The training symbolstorage and generation unit 150 stores the training symbols of a frameto be transmitted at step S12. The controller 130 determines whether aframe data transmission request signal has been received from the MAClayer at step S14. If the frame data transmission request signal has notbeen received from the MAC layer, the controller 130 continues to waitfor the signal. If the request signal has been received, the controller130 transmits a training symbol output request signal to the trainingsymbol storage and generation unit 150, so that the training symbolstorage and generation unit 150 outputs the stored training symbols atstep S16.

While the training symbols are output, the controller 130 outputs a datatransmission request signal requesting the signal field to the MAC layer[the total time required to output training symbols−T_(PROCESS)] afterthe time point at which the training symbols begin to be output at stepS18. The delay unit 110 receives the signal field from the MAC layer,delays the signal field by the processing time of the scrambler 101 atstep S20, and then outputs the delayed signal field to the convolutionencoder 102 at step S22. The controller 130 then transmits atransmission request signal requesting the data field to the MAC layerafter a transmission interval that is set on the basis of the time pointat which the data transmission request signal requesting the signalfield is output to the MAC layer at step S24. The scrambler scramblesthe data field that is received from the MAC layer, and then outputs thescrambled data field to the convolution encoder 102 at step S26.

As described above, in order for the training symbols to be outputimmediately after the frame transmission request signal is received fromthe MAC layer, that is, an upper layer, and in order for the signalfield to be output at the time point at which the output of the trainingsymbols is completed, the controller outputs the request signalrequesting the signal field and the data field to the MAC layer whilethe training symbols are output, in consideration of the total dataprocessing time (T_(PROCESS)) required by the components ranging fromthe scrambler to the guard interval inserter. If the signal field isreceived, the controller performs control so that the delay unit 110delays the signal field by the processing time of the scrambler 101 andthen outputs the delayed signal field to the convolution encoder. Incontrast, if the data field is received, the controller performs controlso that the scrambler scrambles the data field and then outputs thescrambled data field to the convolution encoder. Although not shown inthe drawings, the output of the delay unit 110 and the scrambler 101 isactivated by the controller 130, and the activated interval conforms tothe transmission interval of the transmission apparatus 100.Accordingly, when the training symbols of a preamble, and the data of asignal field and a data field are transmitted, transmission delay can beminimized.

FIG. 15 is a flowchart illustrating an OFDM transmission method for aFIFO operation according to an embodiment of the present invention. Theflowchart shown in FIG. 15 can be preferably implemented in theabove-described OFDM transmission apparatus. The FIFO operationaccording to the present invention is described with reference to theabove drawings and FIG. 15 below.

As described above, the OFDM transmission apparatus 100, including thescrambler 101, the convolution encoder 102, the interleaver 103, theconstellation mapper 104, the inverse fast Fourier transformer 105, theguard-interval inserter 106, the symbol wave-shaping filter 107, the RFconverter 108, the delay unit 110, the controller 130 and the trainingsymbol storage and generation unit 150, exchanges data and signals witha MAC layer, that is, an upper layer, and receives a transmission frame200 from the MAC layer and transmits the transmission frame 200 to thenext stage. The transmission frame 200 is composed of a preamble, asignal field and a data field. Referring to FIG. 15, the controller 130calculates the total data processing time (T_(AFTERFIFO)) of theconstellation mapper 104, the inverse fast Fourier transformer 105 andthe guard-interval inserter 106 that correspond to the componentslocated behind the FIFO unit 140 at step S30. If a frame transmissionrequest signal is received and the output of training symbols begins inresponse to the training symbol output request signal at step S32, thecontroller 130 transmits a FIFO access activation signal to theconstellation mapper 104 [the total time required to output trainingsymbols−T_(AFTERFIFO)] after the time point at which the trainingsymbols are output at step S34. The constellation mapper 104 transmits aFIFO data request signal for reading data to the FIFO unit 140 when theFIFO access activation signal is received at step S36, and thenprocesses data output from the FIFO unit at step S38.

Meanwhile, the conventional transmitter shown in FIG. 4 uses the sameclock for all the function blocks. In order to secure a maximum 54-Mbpsdata rate, a clock close to 80 MHz must be used. If a high-speed clockis used, a heavy load is exerted on the hardware implementation of theinverse fast Fourier transformer. Furthermore, in the OFDM scheme basedon the standard, a transmission bandwidth occupied by the guard intervaland the OFDM symbol is 20 MHz, so that a function block for allowing thedata interval between data strings, which are output from theguard-interval inserter 106 and the training storage and generation unit150, to be 0.05 μs (=1/20 MHz), is required.

This problem can be solved by the following methods.

In a first method, the clock used in the transmission apparatus 100 ofthe present invention uses a multiple of 20 MHz. A 40 MHz clock can beused for a transmission data rate up to 24 Mbps. If the transmissiondata rate exceeds 24 Mbps and is less than 54 Mbps, an 80 MHz clock isused. The training symbol storage and generation unit 105 outputs thesame data twice when the 40 MHz clock is used, and outputs the same datafour times when the 80 MHz clock is used. Furthermore, theguard-interval inserter 106 outputs the same data twice when the 40 MHzclock is used, and outputs the same data four times when the 80 MHzclock is used.

In a second method, the FIFO unit 140 is positioned at a proper locationto separate the clock used to write data into the FIFO unit 140 from theclock used to read data from the FIFO unit 140. This method does nothave a problem implementing the inverse fast Fourier transformer 105 inhardware using a high-speed clock. If T_(PROCESS) approaches 16 μs, itis appropriate to position the FIFO unit 140 in front of the symbolwave-shaping filter 107. Since the clocks can be separated on the basisof the FIFO unit 140, a clock suitable for satisfying a transmissiondata rate is used for function blocks that correspond to the componentslocated in front of the FIFO unit, and a 20 MHz clock is used for thecomponents ranging from the symbol wave-shaping filter that correspondsthe component located behind the FIFO unit. Since at least datacorresponding to the guard interval and the OFDM symbol field must bestored, the load is very heavy in terms of hardware. If the FIFO unit140 is positioned in front of the constellation mapper 104 whenT_(PROCESS) does not exceed 16 μs, the load is lightest in terms ofhardware. Since clocks can be separated on the basis of the FIFOoperation, a clock suitable for satisfying a transmission data rate isused for the function blocks that correspond to the components locatedin front of the FIFO unit, and a 20 MHz clock is used for the componentsranging from the constellation mapper 104 that corresponds the componentlocated behind the FIFO unit. However, as described above, theT_(PROCESS) including the processing time of the FIFO unit 140 must notexceed 16 μs.

In a third method, the first and second methods are appropriatelycombined together. That is, as shown in FIG. 5, the FIFO unit 140 ispositioned in front of the constellation mapper 104, and the clock usedto write data into the FIFO unit 140 and the clock used to read datafrom the FIFO unit 140 are separated from each other. Furthermore, aclock suitable for satisfying a transmission data rate is used for thefunction blocks that correspond to the components located in front ofthe FIFO unit, and clock using a multiple of 20 MHz is used for thecomponents ranging from the constellation mapper that corresponds to thecomponent located behind the FIFO unit. If a 40 MHz clock is used, thetraining symbol storage and generation unit 150 and the guard-intervalinserter 106 output the same data twice. This method can reduce the loadexerted by T_(PROCESS) compared to the second method, and can reduce theload exerted to the hardware implementation of the inverse fast Fouriertransformer compared to the first method. However, as described above,T_(PROCESS) including the processing time of the FIFO unit 140 must notexceed 16 μs.

As described above, according to the present invention, a trainingsymbol storage and generation unit is separated, so that it is possibleto implement an OFDM transmission apparatus having minimal transmissiondelay.

Furthermore, a controller that controls a transmission apparatus using apipeline scheme is used, so that a systematic, efficient OFDMtransmission apparatus can be implemented.

Moreover, an interleaver is implemented to allow the time interval fromthe time point at which data are input to the time point at which theoutput of the data is completed to be the same for all constellationmapping scheme, so that the present invention is advantageous in that itcan mitigate problems occurring at the time of implementing an OFDMtransmission apparatus having minimal transmission delay.

Furthermore, an OFDM transmission apparatus, which is flexible in theuse of a clock, can be implemented using a FIFO device.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

What is claimed is:
 1. An orthogonal frequency division multiplexing(OFDM) transmission apparatus having minimal transmission delay, theapparatus having a scrambler, a convolution encoder, an interleaver, aconstellation mapper, an inverse fast Fourier transformer, aguard-interval inserter, a symbol wave-shaping filter and a RadioFrequency (RF) converter, and transmitting a frame composed of apreamble, a signal field and a data field that are received from a MediaAccess Control (MAC) layer, that is, an upper layer, comprising: atraining symbol storage and generation unit for storing training symbolsfor the preamble, and outputting the stored training symbols when atraining symbol output request signal is received; a delay unit forreceiving data for the signal field from the MAC layer, delaying thereceived data by data processing time of the scrambler, and thenoutputting the delayed data to the convolution encoder; and a controllerfor outputting the training symbol output request signal, requesting thepreamble of the frame, to the training symbol storage and generationunit when a frame transmission request is received from the MAC layer,and outputting a data request signal, requesting the signal field andthe data field, to the MAC layer in consideration of total dataprocessing time (T_(PROCESS)) required by components ranging from thescrambler to the guard-interval inserter; wherein the scramblerscrambles the received data for the data field of the transmitted frame,and then transmits the scrambled data to the convolution encoder.
 2. TheOFDM transmission apparatus according to claim 1, wherein the controlleroutputs the data request signal requesting the signal field to the MAClayer [total time required to output training symbols−T_(PROCESS)] aftera time point at which the training symbols are output from the trainingsymbol storage and generation unit.
 3. The OFDM transmission apparatusaccording to claim 1, wherein the controller outputs the data requestsignal requesting the data field to the MAC layer after a transmissioninterval that is set at a time point at which the data request signalrequesting the signal field is output to the MAC layer.
 4. The OFDMtransmission apparatus according to claim 1, wherein the controllerperforms control so that data of the signal field, which is output fromthe delay unit, can be transmitted to the convolution encoder during aset transmission interval and data of the data field, which is outputfrom the scrambler, can be transmitted to the convolution encoder duringthe transmission interval when the transmission is completed.
 5. TheOFDM transmission apparatus according to claim 1, wherein the controllerreceives information about a data rate and a data length, which iscontained in the signal field, from the MAC layer, and repeatedlygenerates the data request signal requesting the data field at settransmission intervals until the data of the data field corresponding tothe data length are received from the MAC layer according to the datalength.
 6. The OFDM transmission apparatus according to claim 5, whereina length of the data request signal requesting the data field is setaccording to the data rate.
 7. The OFDM transmission apparatus accordingto claim 1, further comprising a First-In First-Out (FIFO) unit that isprovided with dual-port Random Access Memory (RAM) for storing the data,that is placed in front of the constellation mapper, and thatdifferently processes a clock used to write the data into the dual-portRAM and a clock used to read the data from the dual-port RAM.
 8. TheOFDM transmission apparatus according to claim 7, wherein: the delayunit, the scrambler, the convolution encoder, the interleaver and thecontroller, which correspond to components located in front of the FIFOunit, use a clock identical to a clock that is used when data arewritten into the FIFO unit; and the constellation mapper, the inversefast Fourier transformer, the guard-interval inserter, the trainingsymbol storage and generation unit and the symbol wave-shaping filter,which correspond to components located behind the FIFO unit, use a clockidentical to a clock that is used when data are read from the FIFO unit.9. The OFDM transmission apparatus according to claim 7, wherein thecontroller transmits a FIFO access activation signal to theconstellation mapper [total output time required to output trainingsymbols−T_(AFTERFIFO)] after a time point at which the training symbolsare output from the training symbol storage and generation unit when thetotal data processing time of the constellation mapper, the inverse fastFourier transformer and the guard-interval inserter, which correspond tothe components behind the FIFO unit, is assumed to be T_(AFTERFIFO). 10.The OFDM transmission apparatus according to claim 9, wherein theconstellation mapper transmits the data output request signal, whichenables the data stored in the FIFO unit to be output, to the FIFO unitwhen the FIFO access activation signal is received.
 11. An OFDMtransmission method having minimal transmission delay in an OFDMtransmission apparatus, the OFDM transmission apparatus having ascrambler, a convolution encoder, an interleaver, a constellationmapper, an inverse fast Fourier transformer, a guard-interval inserter,a symbol wave-shaping filter and an RF converter, and transmitting aframe composed of a preamble, a signal field and a data field that arereceived from a MAC layer, that is, an upper layer, comprising: thefirst step of calculating total data processing time (T_(PROCESS))required by components ranging from the scrambler to the guard-intervalinserter and storing training symbols of a preamble of a frame to betransmitted; the second step of outputting the stored training symbolswhen a frame transmission request signal is received from the MAC layer;the third step of outputting a data request signal requesting a signalfield of the frame to the MAC layer [total time required to outputtraining symbols−T_(PROCESS)] after a time point at which the trainingsymbols are output; the fourth step of delaying the data for the signalfield, which is received from the MAC layer, by the processing time ofthe scrambler, and then outputting data for the signal field to theconvolution encoder; and the fifth step of outputting the data requestsignal requesting the data field of the frame to the MAC layer after atransmission interval that is set based on a time point at which thedata request signal requesting the signal field is output, and allowingthe scrambler to scramble the received data and then output thescrambled data to the convolution encoder when the data for the datafield are received from the MAC layer.
 12. The OFDM transmission methodaccording to claim 11, wherein output of the data in the fourth andfifth steps step is activated during a set transmission interval. 13.The OFDM transmission method according to claim 11, further comprising:the sixth step of calculating total data processing time (T_(AFTERFIFO))required by components ranging from the constellation mapper to theguard-interval inserter that correspond to components located behind theFIFO unit; the seventh step of transmitting a FIFO access activationsignal to the constellation mapper [total time required to outputtraining symbols−T_(AFTERFIFO)] after a time point at which the trainingsymbols are output; and the eighth step of transmitting a data requestsignal for reading data to the FIFO unit so that the FIFO unit outputsthe data when the control signal is generated.
 14. An orthogonalfrequency division multiplexing (OFDM) transmission apparatus havingminimal transmission delay, the apparatus having a scrambler, aconvolution encoder, an interleaver, a constellation mapper, an inversefast Fourier transformer, a guard-interval inserter, a symbolwave-shaping filter and a Radio Frequency (RF) converter, andtransmitting a frame composed of a preamble, a signal field and a datafield that are received from a Media Access Control (MAC) layer,comprising: a training symbol storage and generation unit that storestraining symbols for the preamble, and outputs the stored trainingsymbols when a training symbol output request signal is received; adelay unit that receives data for the signal field from the MAC layer,delays the received data by data processing time of the scrambler, andthen outputs the delayed data to the convolution encoder; and acontroller that outputs the training symbol output request signal,requesting the preamble of the frame, to the training symbol storage andgeneration unit when a frame transmission request is received from theMAC layer, and outputs a data request signal, requesting the signalfield and the data field, to the MAC layer in consideration of totaldata processing time (T_(PROCESS)) required by components ranging fromthe scrambler to the guard-interval inserter.
 15. An OFDM transmissionmethod having minimal transmission delay in an OFDM transmissionapparatus, the OFDM transmission apparatus having a scrambler, aconvolution encoder, an interleaver, a constellation mapper, an inversefast Fourier transformer, a guard-interval inserter, a symbolwave-shaping filter and an RF converter, and transmitting a framecomposed of a preamble, a signal field and a data field that arereceived from a MAC layer, comprising: calculating total data processingtime (T_(PROCESS)) required by components ranging from the scrambler tothe guard-interval inserter and storing training symbols of a preambleof a frame to be transmitted; outputting the stored training symbolswhen a frame transmission request signal is received from the MAC layer;outputting a data request signal requesting a signal field of the frameto the MAC layer (total time required to output trainingsymbols-T_(PROCESS)) after a time point at which the training symbolsare output; delaying the data for the signal field, which is receivedfrom the MAC layer, by the processing time of the scrambler, and thenoutputting data for the signal field to the convolution encoder; andoutputting the data request signal requesting the data field of theframe to the MAC layer after a transmission interval that is set basedon a time point at which the data request signal requesting the signalfield is output.